Senior Design Verification Engineer - Santa Clara or Remote in the USA
Acceler8 Talent is seeking a Senior Design Verification Engineer to join an extremely well funded start-up that is building fundamentally new technology to extend Moore’s Law beyond the limits of silicon. Backed by pioneers in the field of computing and the world's largest chipmakers, their team has shipped technology used in billions of devices and led development some fo the world's most impactful silicon products.
As a Senior Design Verification Engineer, you will be working on a breakthrough technology that will be used in the first computers to go beyond silicon, focused on verifying memory controllers at top-level.
Key Responsibilities:
● Define and develop verification plans for Top-level and subsystems involving HBM interfaces, Fabrics, memory controllers, PHYs, and custom computing cores.
● Build and maintain UVM-based testbenches to simulate complex SoC/ASIC designs.
● Develop stimulus, checkers, monitors, and coverage models to ensure comprehensive verification.
● Debug RTL and testbench issues using waveform analysis and simulations.
● Collaborate with RTL designers, architects, firmware teams, and system validation engineers to ensure end-to-end functional correctness.
● Drive performance validation scenarios specific to high-bandwidth, low-latency compute workloads.
● Contribute to coverage closure, regression automation, and formal verification methodologies as appropriate.
● Mentor junior engineers and help improve overall verification methodologies and flows.
Required Qualifications:
● B.S./M.S. in Electrical Engineering, Computer Engineering, or related field.
● 5+ years of experience in ASIC/SoC design verification
● Strong knowledge and hands-on experience with UVM and SystemVerilog
● Solid understanding of DRAM, HBM2/2E/3, NOC/Fabric protocols, and memory controller architectures.
● Experience with custom compute core (RISC-V, AI/ML accelerators, DSPs, etc.) integration and verification.
● Familiarity with simulation tools (e.g., VCS, Questa, XSIM) and waveform debuggers (e.g., DVE, SimVision).
● Experience with constrained-random verification, functional coverage, and assertion-based verification.
● Strong problem-solving skills and the ability to work effectively in cross-functional teams.
● Experience verifying at top level, not just block level.
While not essential, any leadership experience or 3rd party vendor management experience would be highly beneficial.
Please apply here or reach out to me at ltomaszko@acceler8talent.com to discuss further.
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